# Busbar Differential Protection (ANSI 87B): High-Impedance vs Distributed Numerical Architecture

> Design comparison between dedicated high-impedance busbar differential schemes with external stabilizing resistors and modern distributed numerical low-impedance systems with CT saturation immunity.

- **Category:** Protection, Control & Automation
- **Author:** Voltformer Substation Protection Engineering
- **Publication Date:** 2026-09-16
- **Reading Time:** 8 min read
- **Key Tags:** #Busbar Protection, #ANSI 87B, #High-Impedance, #CT Saturation, #IEC 60255-187
- **Canonical URL:** https://voltformer.com/articles/busbar-protection-high-impedance-vs-low-impedance-differential-ansi-87b
- **Markdown Source:** https://voltformer.com/articles/busbar-protection-high-impedance-vs-low-impedance-differential-ansi-87b.md

### 1. The Criticality of Substation Busbar Clearing

A short circuit on a substation busbar results in the highest possible prospective fault current ($I_{k}''$ up to $40 - 63\text{ kA}$), as all incoming transmission lines and generation feeders contribute simultaneously into the bus. Protection clearing times must be ultra-fast ($< 15 - 25\text{ ms}$) to prevent switchgear structural destruction and catastrophic system blackout. However, false tripping on an external feeder fault must be unconditionally avoided.

### 2. High-Impedance vs. Numerical Distributed Low-Impedance

| Design Parameter | High-Impedance Differential (87B) | Distributed Low-Impedance Differential (87B) |
|---|---|---|
| **CT Requirements** | All CTs must have identical ratio, low secondary resistance, high knee-point $V_k$ | Accommodates different CT ratios, standard protection cores (5P20, TPX/TPY) |
| **Secondary Wiring** | Direct parallel copper cross-connections to central panel | Dedicated Bay Units (BU) digitize currents; fiber-optic links to Central Unit (CU) |
| **CT Saturation Security** | External series stabilizing resistor ($R_{stab}$) and Metrosil varistor | Sophisticated numerical saturation detectors (directional phase comparison, wavelet) |
| **Busbar Configuration** | Complex auxiliary switch contacts for bus zone switching | Software dynamic zone allocation based on disconnector auxiliary contacts |
| **Breaker Failure (50BF)** | Requires separate external relays and trip relays | Fully integrated 50BF with auto-retrip and zone backup tripping |

The stabilizing voltage calculation for high-impedance protection is:

$$ V_{stab} = I_{f,max} \cdot \frac{N_s}{N_p} \cdot (R_{ct} + 2 \cdot R_{lead}) \quad [\text{Volts}] $$

Where:
- $I_{f,max}$ is the maximum external through-fault current.
- $R_{ct}$ is the secondary winding resistance of the current transformer.
- $R_{lead}$ is the one-way loop lead resistance from the CT terminal box to the relay panel.
- The required external stabilizing resistor is: $R_{stab} = \frac{V_{stab}}{I_{set}} - R_{relay}$.

### 3. Voltage Clamping with Metrosil Non-Linear Resistors

During an internal busbar fault, all saturated CTs feed full current into the high-impedance differential circuit, which would produce destructive kilovolt-level peak voltages ($V_{peak} > 5 - 10\text{ kV}$) across the relay terminals and wiring. A non-linear silicon-carbide **Metrosil varistor** is wired in parallel across the differential circuit to clamp instantaneous voltage spikes safely below $1500 - 2000\text{ V}$ peak without diverting operating current during pickup.

### 4. Protection Engineering Recommendations

- For simple single-busbar industrial substations, high-impedance differential remains exceptionally secure, cost-effective, and mathematically transparent.
- For complex double-busbar, 1.5-breaker, or ring-bus utility transmission substations (110 kV to 400 kV), specify distributed numerical low-impedance systems per **IEC 60255-187-1** to eliminate heavy copper cabling and disconnector switching contact hazards.
- Integrate Breaker Failure Protection (ANSI 50BF) with $100 - 150\text{ ms}$ timer coordinated with breaker mechanism clearing time.
- Supervise CT secondary wiring continuously with sensitive current-unbalance alarms (ANSI 60) to detect open CT circuits before false tripping occurs.

*Reference: IEC 60255-187-1:2021; IEEE C37.234-2020; CIGRE Technical Brochure 824.*

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